The present invention relates generally to communication systems and more particularly relates to an apparatus for and a method of in-band clock compensation for use in synchronous systems comprising one or more processing modules.
The world is currently witnessing explosive growth in the demand for communications networks and systems and it is predicted that this demand will increase in the future. Many communications systems are implemented such that data is transmitted from one component to another an a synchronous manner. For example, data transmitted between nodes in a network may be sent synchronously. In addition, it is common practice to transfer data between cards, i.e. printed circuit boards (PCBs), or modules within a communication device in a synchronous manner.
Transferring data among printed circuit cards in a synchronous system, however, requires that the same clock frequency is used in each card. Typically, each card incorporates its own clock circuit. The clock frequency generated by these different clock circuits may differ in frequency and phase from each other due to inaccuracies in the clock source used which is typically a crystal oscillator that may or may not be temperature compensated.
One prior art solution to this problem is to synchronize the clock circuits on each card in the communications device. This can be achieved using phase lock loop (PLL) circuits or another well-known frequency locking mechanism as described below.
A block diagram illustrating an example of a prior art synchronous communications device is shown in FIG. 1. The communications device, generally referenced 10, comprises ingress data 30 from an input data source and a plurality of modules 20, 22, 28. The modules may comprise any type of functional module, such as a receive module, switch module, transmit module, etc. Note that one of the modules 22 functions as a redundant module. Ingress data is input to the receive module 20 while the output of the transmit module 28 comprises the egress data 32.
Each module includes its own clock source circuitry. To achieve synchronization between cards in the device, all the clock circuits must be synchronized to a reference. The receive module 20 functions as the clock master reference for the plurality of processing modules 22 and transmit module 28. Each module 22, 28 incorporates PLL circuits 26 which function to synchronize their internal clocks to the reference frequency information 24 output by the receive module 20.
A disadvantage of this scheme, however, is that clock compensation is achieved by synchronization of all the clocks on the module internal to the device. This requires additional frequency synchronization circuitry, i.e. PLLs, which increases the complexity and cost and lowers the reliability of the communications device. It also requires the added problem of distributing a potentially high frequency clock source to a number of clock synchronization circuits. A further problem arises, if the module that houses the master clock is removed for any reason, another module must instantly take over and switch clock sources. This is very difficult to achieve and it is likely that one or more modules will experience data loss due to the difference in frequency of the clocks and the resulting difference in timing, FIFO delays processing delays, etc.
Thus there is a need for a mechanism that can compensate for the differences between the clocks in the system that does not require synchronization of all the clocks among the modules in the system.
Accordingly, the present invention provides a novel and useful apparatus for and method of in-band clock compensation. The method of the present invention is particularly useful in synchronous communication systems comprising one or more modules whereby data is transferred between them in a synchronous fashion. Each of the modules comprises an independent clock circuit that functions to generate the one or more clock signals used by the module. The invention provides the compensation between the clocks on different modules so as to enable synchronous communications despite clock source inaccuracies resulting in variations on clock frequency among the different modules.
For illustration purposes, the invention is described in the context of a communications device. Note, however, that it is not intended that the invention be limited to the examples presented herein. It is appreciated that one skilled in the art can apply the principles of the invention to other systems as well wherein a plurality of modules, each having independent clock sources, transfer data in a synchronous manner.
The clock compensation mechanism in each module is operative to compensate for the differences between the clocks among the various modules in the system. Note that the modules may represent printed circuit cards within a single device or may represent separate modules in a larger system or group of modules.
The clock compensation mechanism of the present invention is an in band mechanism wherein special clock compensation or synchronization symbols are inserted periodically into the data stream itself, as opposed to being transmitted external to the data stream. The special symbols are detected by the clock compensation mechanism in each module and the compensation method is performed thereon.
The method comprises adding additional clock sync symbols to the data stream depending on the current level of the FIFO queue on the module or card. If the FIFO level is above an upper threshold, no clock sync symbols are added. This is because a level above the upper threshold indicates that the clock on the current module is slower than that of the reference, thus it is desirable to speed the data through a bit faster to compensate.
If the FIFO level is below the upper threshold but above a lower threshold, one clock sync symbol is added to the data stream. This represents the xe2x80x98do nothingxe2x80x99 decision since a FIFO level in between the upper and lower thresholds indicates that the clock on the current module is essentially even with that of the reference, thus there is no need to compensate the clock in this case.
If the FIFO level is below the lower threshold, two clock sync symbols are added to the data stream. This is because a level below the lower threshold indicates that the clock on the current module is faster than that of the reference, thus it is desirable to slow the data a bit in order to compensate.
Many aspects of the previously described invention may be constructed as software objects that execute in embedded devices as firmware, software objects that execute as part of a software application on a computer system running an operating system such as Windows, UNIX, LINUX, etc., an Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA) or functionally equivalent discrete hardware components.
There is thus provided in accordance with the present invention a method of in band clock compensation for use in a synchronous data processing module, the module including a first in first out (FIFO) queue and adapted to receive an input data stream, the method comprising the steps of inserting a first number of clock sync symbols into the input data stream on a periodic basis, at the module, removing all but a second number of clock sync symbols from the input data stream, determining the level of the queue in the module, if the level is below a lower threshold, inserting a third number of clock sync symbols into the data stream, if the level is above the lower threshold and below an upper threshold, inserting a fourth number of clock sync symbols into the data stream and if the level is above the upper threshold, inserting a fifth number of clock sync symbols into the data stream.
There is also provided in accordance with the present invention an in band clock compensation system for use in a synchronous data processing module, the module including a first in first out (FIFO) queue and adapted to receive an input data stream, the system comprising means for periodically inserting a first number of clock sync symbols into the data stream, means for removing all but a second number of clock sync symbols from the input data stream and symbol stuffing means operative to insert a third number of clock sync symbols into the data stream if the level of the queue is below a lower threshold, insert a fourth number of clock sync symbols into the data stream if the level of the queue is above the lower threshold and below an upper threshold, insert a fifth number of clock sync symbols into the data stream if the level of the queue is above the upper threshold.
There is further provided in accordance with the present invention a method of in band clock compensation for use in a synchronous data processing system, the system including a plurality of processing modules each including a first in first out (FIFO) queue and adapted to receive an input data stream, the method comprising the steps of periodically inserting a first number of clock sync symbols into the data stream before being received by a first module, at each module, removing all but a second number of clock sync symbols from the input data stream, determining the level of the queue in the module, if the level is below a lower threshold, inserting a third number of clock sync symbols into the data stream, if the level is above the lower threshold and below an upper threshold, inserting a fourth number of clock sync symbols into the data stream and if the level is above the upper threshold, inserting a fifth number of clock sync symbols into the data stream.
There is also provided in accordance with the present invention an in band clock compensation system for use in a communications device comprising a receive line card adapted to periodically insert a first number of clock sync symbols into a data stream output therefrom, one or more switch cards, each switch card comprising a first first in first out (FIFO) queue and operative to remove all but a second number of clock sync symbols from the data stream and insert a third number of clock sync symbols into the data stream if the level of the first queue is below a lower threshold, insert a fourth number of clock sync symbols into the data stream if the level of the first queue is above the lower threshold and below an upper threshold, insert a fifth number of clock sync symbols into the data stream if the level of the first queue is above the upper threshold, a transmit line card comprising a second first in first out (FIFO) queue and operative to remove all but a second number of clock sync symbols from the data stream and insert a third number of clock sync symbols into the data stream if the level of the first queue is below a lower threshold, insert a fourth number of clock sync symbols into the data stream if the level of the first queue is above the lower threshold and below an upper threshold and insert a fifth number of clock sync symbols into the data stream if the level of the first queue is above the upper threshold.
There is further provided in accordance with the present invention a clock compensation apparatus for use in a synchronous data processing module comprising an input buffer for receiving an input data stream wherein one or more clock sync symbols are periodically inserted therein, means for removing all but a second number of clock sync symbols from the input data stream, a first in first out (FIFO) queue adapted to receive the input data stream, the system means for inserting a first number of clock sync symbols into the data stream, data processing operative to process the input data stream, a clock compensation mechanism operative to insert a first number of clock sync symbols into the data stream if the level of the queue is below a lower threshold, insert a second number of clock sync symbols into the data stream if the level of the queue is above the lower threshold and below an upper threshold, insert a third number of clock sync symbols into the data stream if the level of the queue is above the upper threshold, an output buffer for outputting the data stream output of the clock compensation mechanism.